Verilog, System Verilog, VHDL, Schematic Simulation, Data Analysis, device physics, Pattern Manipulation, Lab Debug, AI-assisted tools, VLSI semiconductor process, JEDEC specifications

Verilog, System Verilog, Python, software debugging, VHDL, Schematic Simulation, Pattern Manipulation, Data Analysis, internal architecture documentation, schematic layout, circuit simulations, JEDEC specifications for HBM