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Showing 6 jobs
Skills:
Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog
Skills:
Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm
Skills:
Test Plan Creation, Debugging, Python, Perl, VIP integration, testbench architecture, Uvm, verification methodologies, scoreboarding, systemverilog, coverage-driven verification, execution and review, assertions, regression management, debug flows, functional coverage
Skills:
Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification
Skills:
Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog
Skills:
Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM
