C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog, SVA

C, Verilog, Verdi, Xcellium, JasperGold, Uvm, systemverilog

Object Oriented Programming, Shell, Perl, Python, Make file, Power aware verification, Gate-Level Simulation, System Verilog UVM, Mentor, Cadence, UPF, C based and assembly level testcases, Assertions, System Verilog Testbench Architecture, HDL such as Verilog SystemVerilog, Processor Architecture, Processor Verification, HVL such as SystemVerilog testbench OVM UVM, TCI, Synopsys, formal verification, Digital Design

Ethernet, Pcie, Usb, DDR, SPICE-based simulators, LPDDR, MIPI, ESD architecture, ESD circuit design, Spectre, Hspice

Verilog, Usb, Tcl, Arm, System Verilog, Ethernet, Perl, Spi, Ovm, I2c, Python, Soc Architecture, Synthesis, LINT, ASIC design flow, peripheral IPs, Low-power design, Timing Analysis, Axi, BUS Protocols, MBIST, Uvm, Bus Matrix design, MIPS, AMBA, Rtl Design, Timing constraint SDC, DFT concepts, Power estimations, RDC, Formal CDC

C, Tcl, Python, Perl, AHB, GLS, SystemRDL, Uvm, UPF, systemverilog, RAL, IP-XACT, Tk, APB, Axi

layout interaction, silicon bring-up, design sign-off, behavioral modeling, Analog Circuit Design, mixed-signal IC design, post-layout verification, high-speed oscilloscopes, Synopsys Custom Compiler, Spectre, high-speed interfaces, BERTs, Compliance Testing, Parasitic Extraction, Cadence Virtuoso, Hspice