Scripting, EDA Tool Proficiency, Cross-Functional Collaboration, Risk Issue Management, Team Leadership Mentorship, SerDes IP Integration, Architecture Methodology, Technical Ownership Project Planning, RTL-to-GDSII Execution, Advanced Technology Nodes, Stakeholder Vendor Alignment, Timing PPA Closure, SoC-Level Physical Design

Tcl Scripting, Perl, Python, floorplanning, STA timing analysis, PVT analysis, IR EM-related issues, timing ECOs, Cadence Innovus, signoff, Signal Integrity, congestion, CTS routing optimization, full-chip physical design, Timing Closure, setup hold violations, Placement, MMMC SDC constraints, PPA optimization

redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus

Perl, Python, Tcl, primetime, Cadence Innovus, EM analysis, Physical Verification, Signal Integrity, StarRC, Timing Closure, low-power design techniques, Synopsys ICC2

hardware engineering , Clock Tree Synthesis (CTS), Unix, Perl, Linux, Low power verification, floorplanning, Placement, power analysis, PNR implementation, CTS optimization, Optical systems, Equipment and packaging test systems, DSP systems

PPA Optimization, RTL Co-Optimization, Physical Design, primetime, Tempus, Synopsys Fusion Compiler, Cadence Innovus, EDA Tools