THE ROLE:
AMD is seeking a talented, motivated and self-driven digital design engineer to be part of the SerDes Technology group. You will be part of the team developing SerDes/Transceiver designs and solutions. The role involves work on all aspects of the FPGA/ASIC digital design flow including architectural specification, test planning, RTL design, functional verification, through synthesis and implementation to hardware and post silicon validation.
THE PERSON:
The successful candidate will execute digital design work and contribute technically with a high general impact on the overall design. We are seeking a team player who is innovative, highly accurate and detail-oriented, willing to learn, and possessing excellent communication and problem-solving skills to join our design team.
KEY RESPONSIBILITIES:
- Design and development with leading edge technology nodes on digital logic blocks.
- DFT implementation and verification.
- Perform test bench development and functional verification of developed digital logic blocks.
- Perform post silicon validation, testing and debug of block functionality on prototype silicon.
- Work closely with system architect, project manager, design and verification teams to develop design specifications documents, verification plans, and validation test plans.
PREFERRED EXPERIENCE:
- Experience in ASIC or digital IC design, with hands‑on involvement in RTL development (Verilog/SystemVerilog) for complex digital blocks or subsystems.
- Exposure to the front‑end digital design flow, including RTL coding, functional verification, lint/CDC checks, logic synthesis, and timing analysis.
- Experience contributing to one or more ASIC or FPGA tapeouts, either at block or subsystem level.
- Familiarity with DFT concepts and flows hands‑on experience is a plus but not mandatory.
- Exposure to post‑silicon validation, testing, or debug, with an interest in understanding silicon behaviour and root‑cause analysis.
- Background in high‑performance or high‑speed digital designs (e.g., SoC interconnects, memory interfaces, I/O subsystems, data‑path logic) is advantageous.
- Knowledge of SystemVerilog and UVM is a plus.
- Strong problem‑solving skills, willingness to learn new domains (e.g., SerDes/transceiver logic), and ability to collaborate effectively with cross‑functional teams.
ACADEMIC CREDENTIALS:
- Bachelor or Masters Degree in Electronic Engineering.
LOCATION:
Singapore
