Staff Reliability Engineer (Semicon, Wafer Level) x2

Key Responsibilities:

• WLR Methodology & Test Design: Developing and optimizing fast-wafer-level reliability test structures (PCM/WAT) and automated stress algorithms for intrinsic gate dielectric, interconnect, and transistor degradation.

• Intrinsic Reliability Characterization: Executing wafer-level stress testing including Hot Carrier Injection (HCI), Bias Temperature Instability (BTI/NBTI/PBTI), Time-Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Voiding (SM).

• Inline Reliability Monitoring: Establishing WLR inline monitor limits, SPC rules, and screening methodologies to catch process excursions prior to full product burn-in or qualification.

• Process & Integration Co-Optimization: Partnering with Process Integration and Module teams to correlate WLR test results with process marginalities, film stress, plasma damage, and annealing parameters.

• Failure Analysis & Qualification: Directing physical failure analysis (TEM, EMMI, OBIRCH) on WLR failure sites and supporting JEDEC/AEC-Q100 technology qualification vehicles.

Qualifications:

• Education: Bachelor's, Master's, or Ph.D. in Electrical Engineering, Microelectronics, Physics, or Materials Science.

• Experience: 8+ years of hands-on Wafer Level Reliability (WLR) and device physics experience in a semiconductor wafer fab or technology development environment.

If you are interested in exploring this role, or if you have relevant industry contacts who might be interested, please reach out directly with a CV to: [Confidential Information]

EA: 94C3609 | R22105422