Job Description:
- Seize the opportunity to join the team behind the RTL logic design and development of chipsets that power PCs used by millions of people worldwide.
- We're looking for an experienced, disciplined, and highly collaborative IP Logic Design Engineer to join our Chipsets Logic Team (CLIPS) in Singapore. If you're passionate about RTL design and want to work on industry leading client chipsets, this is your chance to make real impact at global scale.
- As an IP Logic Design Engineer, you will:
- Design and develop logic, write RTL, and run formal verifications for IPs that power full-chip designs used across millions of devices.
- Contribute to architecture and microarchitecture definition for next generation blocks.
- Optimize RTL and logic to meet power, performance, area, and timing goals - ensuring high design integrity end to end.
- Review and strengthen verification plans, debug failing tests, and drive corrective actions to ensure feature level correctness.
- Support SoC customers to achieve seamless IP integration and verification.
- Ensure high quality IP to SoC handoff through strong quality assurance practices.
- You'll be part of a high impact engineering team shaping the future of client chipsets while working in a collaborative and growth driven environment.
Minimum Technical Requirements:
- 12+ years of hands on experience in pre-silicon verification or RTL logic design.
- Expertise with SystemVerilog, scripting languages (Python/Perl/Shell/etc), power-aware simulation flows (VCS/Synopsys tools), RTL model builds, and DFT/DFV methodologies.
- Experience developing test plans, coverage strategies, and validation content aligned to high level silicon or IP architecture specifications.
- Familiarity with VLSI design flows, including structural and physical design processes, as well as SIP/HIP interoperability.
- Strong background in power-aware design and verification in modern low power semiconductor products.
Preferred Technical Skillsets:
- Experience with industry standard semiconductor bus and interface protocols such as AMBA, MIPI, USB, and PCIe.
- Solid understanding of chipset or CPU level power behavior, including power estimation and low power design techniques widely used in semiconductor products.
- In-depth expertise with PCI Express, including PCS, FEC, LTSSM, and high-speed data path microarchitecture for advanced silicon generations.
- Deep knowledge of high-speed digital design, achieving timing closure at GHz frequencies using pipelining, retiming, and advanced microarchitectural techniques experience with synthesis, STA constraints, and timing analysis in semiconductor flows.
- Experience implementing low power optimization techniques such as clock gating, power gating, and power domain design.
