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THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's SERDES IP, resulting in no bugs in the final design.
THE PERSON:
The ideal candidate should have a deep understanding of analog design and able to lead, attend, and present at design review meetings with teams worldwide.
KEY RESPONSIBILITIES:
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
Job ID: 151327401
Skills:
clock distribution , Pll, transmitter front-end, serializer, Analog Design, Circuit Design, receiver front-end, wireline transceiver building blocks, deserializer, high speed analog design, FinFET technology
Skills:
clock distribution , Pll, transmitter front-end, serializer, Analog Design, Validation, wireline transceiver building blocks, receiver front-end, deserializer, high speed analog design, Circuit Design, FinFET technology
Skills:
clock distribution , Pll, transmitter front-end, serializer, Analog Design, receiver front-end, wireline transceiver building blocks, deserializer, high speed analog design, Validation, Circuit Design
Skills:
clock distribution , Pll, transmitter front-end, serializer, Analog Design, deserializer, wireline transceiver building blocks, receiver front-end, high speed analog design, FinFET technology, Validation, Circuit Design
Skills:
clock distribution , Pll, transmitter front-end, serializer, Analog Design, receiver front-end, deserializer, wireline transceiver building blocks, high speed analog design, FinFET technology