THE ROLE:
The AMD SerDes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an experience analog/mixed-signal layout design engineer to join our world-class team in the development of SerDes solutions to facilitate the future connectivity of AMD CPU and GPU products.
THE PERSON:
You have a passion for high speed layout design with innovative and creative ideas to solve complex design challenges. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills, and are willing to learn, and ready to take on problems.
KEY RESPONSIBILITIES:
- Layout design of high speed and high performance SerDes analog mixed signal circuit in accordance to project requirements and specifications.
- Block level physical implementation which includes floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout.
- Participate in post-layout circuit performance analysis.
- Participate in block/IP/chip level integration activities.
- Estimate realistic schedule, track and report clear progress and status.
- Strong participation in defining layout methodology and flow.
- Driving layout productivity improvement initiatives (i.e., pcell development and automation).
- Other responsibilities which include supervision of layout resources (onsite and offsite), assessing and correcting layout quality issues, and providing feedback to design teams.
PREFERRED EXPERIENCE:
- Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating.
- Good understanding of high speed critical signal routing and shielding.
- Strong in physical design verifications (LVS/DRC/ERC/ANT/ESD/etc.).
- Familiarity with circuit design concepts/flows and IC manufacturing processes.
- Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process is a plus.
- Experience with digital on top integration flow or digital SOC flow is a benefit.
- Experience with Cadence SKILL and other programming is a benefit (Perl, Python, Tcl, etc.).
- Ability to work closely with the remote & different time zones design teams.
- Excellent team player and good communication skills.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer Engineering/Electrical Engineering.
LOCATION:
Singapore
