(Sr./Staff) System Engineer - Edge AI & Systems

Job Description

We are looking for multiple seasoned Senior and Staff System Engineers to grow an Edge AI & Systems software team to the next level. This team works within the larger ASIC team to architect and enhance Neural Network solutions in the Video Processor roadmap including these current and older products:

• https://www.ovt.com/products/oax8000/
• https://www.ovt.com/products/oax4600/
• https://www.ovt.com/products/oa7100/

Deliveries:

• Neural Network Processor (NPU) architecture, programming Model, simulation, verification, profiling and optimization
• Specification, review and verification of other IP blocks
• FPGA images and IO boards for pre-silicon verification and design exploration
• Boot ROM, bare metal BSPs, sample applications

Responsibilities:

• Support Inference Engine, Toolchain and ASIC teams on NPU
• Constantly improve productivity through automation in all areas

Skills:

• Strong ANSI C bare-metal design, implementation, optimization and debugging using GCC-like toolchains
• Strong processor architecture knowledge: ARM/RISC-V ISA, symmetric multiprocessing, cache architecture, SIMD, Vector Processing, custom instructions
• Strong software, hardware and FPGA debugging capability
• Good communication, collaboration, task estimation & reporting, CI/CD via tools such as Confluence, Git, JIRA etc
• Familiarity with
• Python for prototyping, demo, verification and/or automation
• OS: GNU/Linux, proprietary RTOS, Bare metal

The following will be advantageous:

• Detailed and comprehensive understanding of TinyML (e.g. TensorFlow Lite for MCUs), from training, quantization through to operator execution, optimizing for power, performance, and size.

Requirements:

1. Ph.D/MSEE/BSEE in Electrical Engineering, Computer Science or Computer Engineering
2. At least 5 years of commercial embedded system architecture and development experience.
3. Experienced in fixed point computing implementation strategies, such as quantization, scaling, saturation and overflow handling.
4. Design, implement, and maintain high-quality C/C++ functional & bit-Accurate Model for NPU operation simulation