Build verification platforms and complete IP / SOC-level verification work, such as Memory Controller (DDR, HBM, 3DDRAM, etc.), Noc, PCIe, UCIe, and SoC.
Participate in the review and optimization of the microarchitecture design of each subsystem, develop detailed module level and SoC level test plans for all the functional features, based on the design spec.
Develop directed and constrain-random verification functional tests to complete SoC/IP functional verification and performance verification.
Communicate with the software team to build the performance benchmark of Soc, develop performance cases to count bandwidth and latency, and assist design in analyzing performance bottlenecks and performance optimization.
Within the scope of security compliance, use AI-assisted verification and process automation to improve verification efficiency.
Strictly follow the development process and quality specifications to ensure that development work is completed on time and to the required quality, ultimately achieving successful tapeout.
Qualifications:
Bachelor/Masters in computer, electronics, semiconductor or related majors, 3+ years of verification experience, with tapeout experience preferred.
Familiar with Memory Controller(DDR, HBM, 3DDRAM, etc.), Noc, bus, PCle, UCIe, etc., and familiar with verification processes and specifications.
Familiar with AI chip architecture, NoC bus architecture, AMBA bus protocol, and familiar with PCle and UCIe protocols.
Familiar with LPDDR/GDDR/HBM protocols and DFI protocol, understand the entire post-power-on initialization process.
Experience in supporting post-silicon test vector generation and failure analysis. Experience preferred.
Within the scope of security compliance, use AI-assisted verification and process automation, with preference given to those with experience.
Proficient in Systemverilog/UVM, familiar with Python/scripting languages, and Makefile.
Strong communication, analytical and documentation skills and ability to interface with other groups.
Preferred Skills
Successful tapeout experience in areas such as Memory (DDR, HBM, 3DDRAM, etc.), chip interconnect NOC, PCle, UCIe, etc.; AI-assisted verification.
