Bachelor of Science in Electrical Engineering with 8-10 years of relevant work experience, or Master of Science in Electrical Engineering with 6-8 years of relevant work experience preferred.
Strong understanding of high-speed SERDES, equalization technique and any high-speed standard (IEEE802.3, PCIe, DP, etc.)
Proven experience in High-Speed IO testing, debugging and validation, strong lab skills with hands on experience, in system bring up, system testing and debug.
In-depth working knowledge of test equipment used for SERDES characterization (Scope, BERT, Network analyzer, etc.).
Working knowledge of IEEE 802.3 400G/800G/1.6T interface and characterization
Working knowledge of board design able to read board schematics and board layout.
Knowledge in SERDES modeling techniques and proven experience working with Perl or Python.
Working knowledge and experience on PCIe and/or SAS/SATA SERDES and extensive knowledge of the physical and protocol levels (PIPE I/F, PCS, MAC) of one or more common high-speed interfaces is a definite plus.
Job Responsibilities
Complete responsibility of PHY Validation in post-silicon environment
Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices
Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality
Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER
Analyze and debug issues on Phy protocol of storage interface (SATA, SAS, PCIe, Ethernet)
