Job Responsibilities:-
- Perform Design synthesis with Synopsys/Cadence toolset, with full knowledge and understanding of functional constraints
- Create timing constraints for functional, DFT modes for synthesis/STA by working closely with Design and DFT Engineers
- STA/timing closure
- Write Low power intent file (CPF/UPF) from specification and verifying correctness of power intent file using CLP/VCLP
- Perform Logic equivalence checks
- Work with physical design engineer to resolve all netlist and timing issues
Job Requirements:-
- Master's/Bachelor's Degree in Electrical/Electronics Engineering with an emphasis in IC design with at least 12 years and above of related working experience
- Good experience with Synopsys tool suite or Cadence toolsuite
- Proficient in TCL scripting, python knowledge is a ++
- Able to work in a team with a strong drive to excel
- Able to work independently on a given assignment and work hard to finish on time
- Good written and communication skills
Location: Next to Bendemeer MRT
Interested candidates may submit detailed CV with the following info:-
- Current salary, including AWS or Variable Bonus
- Expected salary
- Availability
