Lead the development of high-speed, high-performance SerDes IP in advanced technology nodes (5nm, 3nm, and beyond).
Design complex IP blocks including, but not limited to, 112G/56G PAM4, 32G PAM2, DDR, Die-to-Die High-Speed Interconnect, and System PLL IPs.
Collaborate with DSP, analog, and digital design teams on SerDes architecture definition and implementation.
Provide clear design guidance and technical direction to layout engineering teams.
Partner with application engineers to define and execute IP characterization and validation plans.
Support lab bring-up, characterization, and debug of SerDes IPs.
Collaborate closely with product and customer teams to ensure seamless integration and robust performance.
What We're Looking For
What You Bring to the Role:-
Bachelor's Degree in Electrical Engineering with 3-5 years of relevant experience, or a Master's Degree with 1+ years of experience PhD in Electrical Engineering is also welcome.
Hands-on experience in high-speed analog mixed-signal design at 7nm process nodes or below.
Strong background in PAM4, 56G, or 112G SerDes design is highly desirable.
Proven understanding of high-performance SerDes architecture and development.
Effective team player who thrives in a collaborative, cross-functional environment.
Experience in project leadership and SoC integration support is a plus.
Committed to continuous improvement and helping others excel.
