We are looking for a Senior Design Verification Engineer to work on Espressif's next-generation wireless and AI-capable SoCs. You will work closely with RTL designers and chip architects, and provide technical leadership within a small verification sub-team.
Job Responsibilities
- Define verification plans and test cases based on design specifications, and own the verification environment end-to-end
- Collaborate with design engineers to identify and resolve design defects, and continuously drive verification coverage improvement
- Maintain simulation/verification environments using industry-standard EDA tools
- Write scripts to automate testing workflows in Python, Perl, TCL, or Shell
- Track and report code/functional coverage metrics; identify and close gaps before tapeout
- Debug failures and root-cause issues, working closely with designers to resolve issues
- Leverage AI tools to optimize verification flows and improve team-wide efficiency
- Mentor junior verification engineers and provide technical guidance across the team
Job Requirements
- Bachelor's degree or above in Electronic Engineering, Computer Engineering, Computer Science, or a related field
- Preferably 3+ years of ASIC/SoC/IP design verification experience
- Proficiency in Verilog, SystemVerilog, UVM, and C
- Proficiency in scripting languages such as Python, Perl, Shell, or TCL
- Strong interest in exploring and adopting AI tools to improve day-to-day engineering productivity and verification efficiency
