Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;
Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support; SoC verification plan and SoC verification support
Job Requirements
Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
Experience with ASIC design flow
Experience in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure and verification
Good understanding of DFT
Familiar with UNIX/ Linux environment and scripting
