Research Engineer / Research Associate (FPGA Prototyping and ASIC Design Flow)

About TUMCREATE

TUMCREATE is a multidisciplinary research platform of the Technical University Munich (TUM) at the Singapore Campus for Research Excellence and Technological Enterprise (CREATE). We are joining forces with universities,public agencies, and industry for the advancement of future technologies.

Please visit www.tum-create.edu.sg for more information about TUMCREATE.

Job Purpose/Objective of the Position:

TUMCREATE is seeking a researcher/engineer to join the QUASAR project, focusing on bridging FPGA-based system prototyping with manufacturable chip design, enabled by open-source EDA toolchains and design automation methodologies.

This role is not a conventional FPGA or ASIC role - it targets candidates interested in cross-layer co-design, from architecture and RTL to physical implementation.

This is a fixed term contract until March 2029 when applicable.

QUASAR Project Overview:

The QUASAR project focuses on implementing Post-Quantum Cryptography (PQC) within the RISC-V ecosystem. This is a high-stakes, cutting-edge initiative designed to secure future digital infrastructure against quantum threats. QUASAR is a collaborative effort between Fraunhofer, Technical University of Munich (TUM), Nanyang Technological University (NTU), and National University of Singapore (NUS), fostering long-term research collaboration and talent development in quantum security.

Job Responsibilities:

• FPGA System Design & Prototyping

Collaborate with FPGA researchers to implement and validate complex RTL systems on FPGA platforms

Integrate and customize RISC-V-based cores and SoC subsystems

Develop FPGA-based prototypes for architecture validation and early design exploration

Optimize designs for FPGA constraints(timing, resource utilization, memory hierarchy)

• Open-Source EDA Tool Development &Flow Integration

Customize and integrate tools such as Yosys, OpenROAD, OpenLane, Verilator, etc.

Develop scripts and modules for automated RTL-to-GDS flows, constraint generation (timing, floor planning, pin assignment), and design space exploration.

Improve robustness of open-source flows by debugging synthesis and mapping issues, etc.

Contribute new algorithms or heuristics in areas such as physical design optimization.

• FPGA-to-ASIC Transition & Chip Design

Translate FPGA-validated designs into ASIC-ready implementations

Work with open-source flows to perform synthesis and physical design

Support the generation of manufacturable layouts in open-source technology nodes

Job Requirements/Competencies:

• Degree in Electrical Engineering,Computer Engineering, Computer Science, or related fields
• Strong foundation in digital design (RTL, timing, pipelining)
• Hands-on experience with FPGA design flows
• Familiarity with RISC-V architecture or SoC design
• Programming skills in C/C++ and/or Python
• Preferred Qualifications:

Experience with open-source EDA tools (e.g., Yosys, OpenROAD, OpenLane)

Understanding of ASIC design flow (synthesis → P&R → signoff)

Experience in EDA tool development or design automation

Interest in cross-layer optimization(architecture ↔ physical design)

What TUM CREATE offers you

• Hands-on experience with a state-of-the-art open-source RISC-V core on FPGA
• A well-established FPGA platform with a clearly defined research scope
• Close supervision within an international, interdisciplinary research project
• A collaborative and inclusive world-class research environment
• Competitive salary that commensurate with experience
• Medical insurance
• Good amount of leave/vacation days
• Vibrant, modern and positive working environment in Singapore
• Campus-sited office location with a host of facilities
• In-building perks including gym, game room and coffee room

Applications

Please send your complete application,including cover letter (compulsory), CV, university transcripts (compulsory) to [Confidential Information].

Only shortlisted candidates will be contacted.

We look forward to your application!