Focus on silicon photonics chip yield improvement, be responsible for yield-related quality control in the design stage, participate in reviews, identify design-end yield risks and put forward optimization suggestions.
Lead yield control in the NPI process, formulate test and verification plans, dock with each production station to ensure controllable trial production yield and lay the foundation for mass production.
Optimize product design specifications and quality standards, match production processes with yield improvement needs, and reduce design-related yield loss.
Track yield and quality data during trial production and initial mass production, analyze low yield issues related to design, promote design improvement, and continuously improve product yield.
Cooperate with FA, PQE and other positions to analyze design-related failure cases affecting yield, output and track improvement plans, and reduce yield loss.
Participate in quality and yield reviews, summarize design-end yield data, summarize improvement rules, and promote continuous optimization of product design.
Any other ad-hoc tasks as assigned.
Requirements:
Minimum Bachelor's Degree in Electronic Engineering or related majors
Minimum 3 years of silicon photonics/semiconductor design quality experience, yield improvement experience is preferred.
Familiar with silicon photonics chip design principles and manufacturing processes, master tools such as DFMEA and DOE, with strong yield analysis and design optimization capabilities.
Participated in the whole NPI process of silicon photonics chips, able to independently formulate design quality control plans based on yield improvement.
Strong communication and coordination skills, able to cooperate with various departments to promote yield improvement at the design level.
Familiar with ISO9001 system, with good English proficiency to understand design and yield-related documents
