To liaise with module engineers on defect excursion control
To drive for defect reduction and yield improvement activities
Job Description:
Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operati
Train and certify YE Associate Engineers on recipe creation and defect source knowledge
Maintain and enhance internal SOP/OCAP and involve in internal/external audit
Operate FIB/SEM/EDX/OM for inline failure analysis
Operate and create recipes in Brightfield, Darkfield and other defect inspection tool
Perform partition analysis on defect source and detailed reports on issues
Build and develop defect source library.
Track inline defect performance by layer/process tool/chamber on weekly basis
Perform killer ration analysis
Perform defect characterization by process tools
Continuous improvement activities on defect reductions with Modules / vendors / equipment team
Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities
Provide scan support in low yield investigation & co-work with Module/PI/PE on technology & device specific yield enhancement activities
Automate daily activities to improve troubleshooting speed of team
Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems
Job Requirements:
Masters / Degree in Electrical and Electronic Engineering/ Microelectronics Engineering / Material Science / Chemical Engineering / Electronic and Physics
5 - 8 years relevant fab work experience in high volume manufacturing of electronics components in an Front-end semi-conductor industry.
Experience in defect analysis and yield enhancement in wafer process.
Excellent interpersonal and communication skills with good leadership capability.
Team player.
Strong analytical skills and able to work under pressure in a fast pace environment,
Proficient with MS Power Point, Excel, Excel VBA, PowerBI
