Principal Design Engineer
Search Jobs
Search by job, company or skills
Search by job, company or skills
Job ID: 148088209
Skills:
constraint analysis , Perl, Verilog, System Verilog, Tcl, Sta, Synthesis, Simulation, synthesis logic equivalence, timing constraints generation, STA tools and flow, design for test, IP ASIC timing constraints generation, Dft, formal verification, backend related methodology and tools, LINT, Timing Closure, Design Methodologies, functional coverage, timing closure of various test modes
Skills:
Phase Interpolator, SERDES, Driver, Circuit Simulation, Physical Verification, Deserializer, Layout, CMOS design, Bias and Bandgap Voltage Regulators, Receiver, jitter and signal equalization techniques, High Speed Clock Distribution, Serializer, Low jitter PLL
Skills:
Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Physical verifications, Pll, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check
Skills:
Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Pll, Physical verifications, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check
Skills:
hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, C Language, Scan dump, DFT architecture
