Physical Verification Design Engineer- LVS

Perform Layout Versus Schematic (LVS) checks to ensure consistency between schematic and layout designs

Identify, debug, and resolve LVS errors in collaboration with design and layout teams

Support physical verification processes including DRC (Design Rule Check) and ERC (Electrical Rule Check)

Work closely with layout and circuit design engineers to ensure design accuracy and manufacturability

Assist in improving LVS runsets, flows, and verification methodologies

Document verification results and report issues in a timely manner

Requirement:
Bachelor's degree in Electrical Engineering, Electronics, or a related field

2 years of experience in semiconductor/IC design

Basic understanding of IC design flow and physical verification concepts

Familiarity with EDA tools such as Cadence (Virtuoso), Mentor Graphics (Calibre), or Synopsys tools

Strong analytical and problem-solving skills

Good communication skills and willingness to learn

EA:25C2690 R23115755