Physical Design Engineer
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Job ID: 145500537
Skills:
Perl, Python, Tcl, power analysis, Cadence ARP tools, low power checks, Timing Analysis, RTL to GDS implementation, block-level timing closure
Skills:
Perl, Python, Tcl, power analysis, Cadence ARP tools, low power checks, formal checks, RTL to GDS implementation, block-level timing closure
Skills:
power integrity , Physical Design, electromagnetic compatibility, Cadence Innovus, Logic Synthesis, Physical Implementation, Synopsys ICC2
Skills:
Partitioning, floorplanning, Cadence Innovus, Cross-block timing closure, Synopsys ICC2
Skills:
Physical Design, Partitioning, floorplanning, Cadence Innovus, Cross-block Timing Closure, Physical Implementation, Synopsys ICC2
