Physical Design Engineer

Responsibilities

• Perform end-to-end digital physical design implementation (RTL to GDS)

• Execute full-chip STA signoff, contribute to STA signoff methodology, and run SPICE simulations for critical timing paths.

• Develop, optimize, and maintain physical verification, power integrity, and STA flows, supporting new EDA tools and advanced process technologies.

• Support PPA (Power, Performance, Area) and yield optimization through flow improvement and tool enhancement.

• Collaborate with cross-functional teams to ensure successful tape-out and design closure.

Requirements

• Strong hands-on experience with full digital physical design flow (RTL to GDS) and EDA tools such as Innovus, Fusion Compiler, PrimeTime, PrimePower/PX, RedHawk, Calibre, etc.

• Solid expertise in STA analysis methods and signoff flows familiarity with DC or FC synthesis.

• Experience in top-level power integrity, physical verification, bump, or ESD planning is advantageous knowledge of signoff standards for advanced process nodes is preferred.

• Proven tape-out experience, especially with ultra-low-voltage, large-scale, or complex IP designs, is highly advantageous.

• Familiar with low-power design methodologies, power analysis, and PPA optimization.
• Strong scripting/programming skills in Tcl, Python, Perl, C, or C++.

• Exposure to 3D IC design is a plus.
• Prior experience supporting STA signoff in tape-out projects is preferred.

If interested, please submit your application to [Confidential Information] with your expected salary and resume.

We regret that only short-listed candidates will be contacted shortly. By submitting your application or resume, you agree to the collection, use, retention, and sharing of your personal information with potential employers for their assessment.

JDA WMS Pte Ltd | EA Personnel: Pham Thi Tuyet Mai

EA License No: 23S1595 | EA Registration No: R25127838