Responsibilities
- Design physical layouts for advanced process digital ASIC, AI, and CPU chips to meet performance and manufacturing requirements
- Execute layout design for analog and digital chips, ensuring precision and compliance with specifications
- Optimize power, performance, area, and cost (PPAC) under advanced semiconductor processes
- Perform full custom design tasks and investigate new technologies in advanced packaging to enhance chip capabilities
- Implement back-end physical design from gate-level netlist to GDSII, including placement and routing (PR), parasitic extraction (PV), and IR drop signoff
- Conduct static timing analysis (STA) and Spice simulations to verify design timing and electrical integrity
- Collaborate with cross-functional teams to ensure design meets signoff criteria and production readiness
Preferred competencies and qualifications
- Bachelor's degree or higher in Mathematics, Physics, Electronic Science and Technology, Microelectronics, Information and Communication Engineering, Computer Science and Technology, or Materials Science and Engineering
- Strong theoretical foundation in digital circuits and practical skills in IC development processes
- Demonstrated curiosity, rapid learning ability, and capability to transfer knowledge across related professional fields
