Responsible for analog/hybrid circuit program planning and design implementation, performance optimization, simulation verification and testing related work
Responsible for the design of high-performance, ultra-low voltage customized circuits under advanced technology. Targeting specific PPA requirements, able to select transistors, layout
Effect analysis, unit logic merging and simplification, and starting from the underlying optimization thinking, deliver digital units or modules that can be integrated
Responsible for the physical design, analog/digital chip layout design of advanced technology digital ASIC/AI/CPU chips, and the exploration of new technologies such as PPAC optimization, fully customized design, and advanced packaging under advanced technology
Write various design documents and standardized materials, and implement the company's development processes, specifications and systems.
Work tasks include but are not limited to:
Commonly used analog chip or IP design, transistor-level circuit design and simulation, layout planning and design, timing library characterization extraction, SRAM custom design, etc.
From gate-level netlist to back-end physical implementation of GDSII, digital/analog chip layout design, including PR, PV, IR Signoff, PPAC optimization, Sta/Spice Signoff, etc.
Chip design process development, In-House EDA tool development, chip yield tracking and optimization
Requirements:
Majors include but are not limited to mathematics/physics/electronic science and technology/microelectronics/information and communication engineering/computer science and technology/materials science and engineering fresh college students or overseas students within one year of graduation , master's degree or above
Excellent academic performance, strong curiosity, learning ability and knowledge transfer ability for new things and knowledge in professional and related fields
Understand the IC development process, and have a certain theoretical foundation and necessary capabilities of digital circuits as well as innovation capabilities.
