Photonics Test Engineer #EEF

.Responsible for silicon photonics chip design, simulation, and layout implementation

.Based on the SOI/CMOS process platform, complete link-level modeling, layout design, and verification of key devices such as silicon-based modulators and detectors

.Responsible for chip-level signal integrity (simulation and test verification), addressing issues related to high-speed parasitics, crosstalk, and packaging losses

Elsa Fontanne (CEI No. R24124496)

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