PCIe PHY Validation Lead

Role Overview

Lead end-to-end PCIe PHY validation for advanced AI, cloud, connectivity, and compute platforms. Own silicon bring-up, electrical characterization, compliance readiness, interoperability, system-level debug, and production validation. Act as the technical authority across PHY, SI/PI, firmware, board, package, and system teams.

Key Responsibilities

• Own PCIe PHY validation strategy, plans, coverage, and execution from pre-silicon through production.
• Lead hands-on electrical characterization of TX/RX, reference clock, reset, equalization, lane margining, jitter, and channel performance.
• Perform PCIe bring-up and debug using LTSSM analysis, register dumps, firmware logs, protocol traces, and electrical measurements.
• Analyze eye diagrams, jitter, presets, CTLE/DFE, SSC, de-emphasis, insertion/return loss, crosstalk, and channel margin.
• Drive compliance and interoperability testing, including failure reproduction and closure of compliance gaps.
• Correlate simulation, lab measurements, and system behavior to identify PHY, board, package, firmware, or platform issues.
• Partner with silicon design, firmware, SI/PI, board, manufacturing, and customer-facing teams.
• Mentor engineers and provide technical recommendations to engineering leadership.
• Develop automation and data-analysis tools using Python, instrument APIs, register access, and log parsing.

Ideal Requirements

• Extensive hands-on experience with PCIe PHY or high-speed SerDes validation at silicon, board, or system level.
• Strong practical experience with oscilloscopes, BERTs, protocol analyzers, VNAs/TDRs, pattern generators, compliance tools, and high-speed probes.
• Deep understanding of PCIe electrical concepts, including jitter, eye margin, equalization, presets, CTLE/DFE, SSC, channel loss, and crosstalk.
• Proven system-level debug experience across PHY, firmware, BIOS, host platforms, retimers/redrivers, connectors, PCB, power, and thermal conditions.
• Strong Python, automation, data analysis, and lab scripting capabilities.
• Working knowledge of S-parameters, channel modeling, SI/PI, package/board effects, and simulation-to-measurement correlation.
• Experience with Linux bring-up, low-level register debugging, and firmware-controlled PHY tuning.
• PCB/package layout knowledge with Cadence Allegro, APD, or similar tools is a plus.
• Strong cross-functional leadership, problem-solving, communication, and mentoring skills.