Job Description
Job Description:
Job description:
Responsible to understand and apply all necessary layout guidelines (standard cells, I/O), new process rules and other technical requirements for quality layout.
Schedule time-line & layout floor-planning
Complete quality layout and verification within planned schedule (without supervision for experienced engineer)
Get up to speed quickly for new methodologies, open to new ideas and communicate well with others in the library team
Skill Set / Requirements:
Bachelor Electronics engineering graduates with minimum 2 years of layout experience.
Experience in standard cells or full custom and/or analog layout design and physical verifications includes LVS, DRC, ERC, Antenna, Electro Migration (EMIR) in Finfet, CMOS process.
Good experience in Floor-planning, hierarchy layout and chip integration.
Experienced in Cadence Layout tools VIRTUOSO (XL, VXL or EXL), and CALIBRE verification tools.
Good understanding of Latch-up and ESD in CMOS process and implementation for IO layout design.
Good understanding of hierarchical, memory layout topology and memory bitcell design flow for implementation in memory compiler.
Knowledge of Script Programming and SKILL Programming would be a plus.
Self-reliant, with ability to work independently as well as a team.
Strong layout knowledge in advance process, e.g. 5nm, 3nm, 2nm
R024266
