FE CPIE CPI Senior Engineer/Engineer

As Front End Central Product Integration Engineer-Chip Package Interaction at Micron Technology, Inc., you will be responsible for working with global Micron network to drive each silicon node's Packaging Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution.

In addition, you will be responsible in integrating solutions by connecting cross-functional expertise, standardizing the business process and regularly benchmarking internal and external intelligence to achieve the highest value bits and productivity.

Responsibilities and Tasks

• Promote worldwide synergy for improved benchmark performance and efficiency gains through global project management and execution, network BKM leveraging and enhancement, and business process creation and re-engineering.

• Define strategies to ensure that Packaging Technology and interaction with Front End manufacturing process are fully developed and qualified well ahead of any qualification of the product itself.

• Lead the PI Loop taskforce and/or team in network to address yield and quality challenges, optimize process flow in a timely manner to achieve BIC yield performance.

• Maintain and enhance domain knowledge and technical expertise, explore innovation opportunities with strategic thinking and systematic approach.

• Maintain a strong and open relationship with peer group and managers in other functional areas within central team and outside in areas such as Fab, TD, Product Engineering, GQ. Communicate and respond to issues in a timely manner. Help drive to fix the issue where necessary.

• Demonstrate ability to give effective presentations to both small and large groups on project updates and new initiative proposals.

• Periodically follow up with manager to ensure all type of goals are met and get assistance to remove obstacles.

• Travel to Micron Fab locations as necessary for face-to-face work.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Microelectronics, Physics, Chemistry, Material Science Engineering or related field

• A minimum of 2 years of experience in Back-End-of-Line (BEOL) semiconductor processing or process integration is required

• Must be willing to travel as needed to support departmental goals, with an expected travel frequency of approximately 20-50%

• Knowledge in Semiconductor Device Physics, DRAM operations, wafer fabrication process flows, parametric/electrical test and probe yield.

• The experience on DRAM HPM, BEOL integration, advanced packaging and layout will be a plus to this job position.

• Good data analysis, troubleshoot, problem solving, reporting and presentation skills with a strong attention to detail.

• Good multi-tasking, verbal, and written communication skills.

• Strong interpersonal skills and customer/co-worker relationships. Successfully demonstrated teamwork skills with a strong focus on developing good team dynamics.

• Good organizational capabilities and ability to work effectively with minimal supervision.

• Intermediate to advanced PC skills including Microsoft Office.

• Ability to be flexible with job responsibilities and take the initiative to assume added responsibilities.

  Maximizes yield by working on tools, the process, or wafer fabrication recipes. Troubleshoots wafer fabrication problems and performs root cause analysis. Works with other process areas to understand and control process deviations. Long-term investigation of defect issues may require extensive work with shift engineering and other functional areas. Evaluates products to ensure they meet the required design and performance specifications. Conducts research to assess process adjustment requirements and recommends process improvements or equipment changes needed to efficiently manufacture new product or part types.