Develop verification plans based on design documents, define module-level verification strategies, build verification environments and frameworks, and complete both module-level and chip-level verification
Execute regression testing to improve verification coverage
Work with chip design engineers to identify and fix design defects ensure the completeness of chip design and guide the design team to follow a verifiable design process
Conduct gate-level simulation and formal verification with UPF to ensure successful tape-out
Job Requirements:
Bachelor's degree or above in Computer Engineering, Electronic Engineering, Communications Engineering, or related fields
Ideal candidates will have at least 3 years of professional experience
Familiarity with digital SoC or communication module principles
Familiar with Verilog and proficient in C / SystemVerilog for verification
Proficient in scripting languages such as Perl / Shell / Tcl
