Digital IC Design Engineer (RTL/Verilog/Logic Synthesis/DFT) LT93

5-7 Years

SGD 7,000 - 8,500 per month

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Early Applicant

Job Description

Key Responsibilities

Develop and implement Verilog/VHDL RTL designs based on product specifications
Perform logic synthesis and static timing analysis (STA)
Collaborate with physical design teams to achieve timing closure
Work with system and software teams on FPGA-based verification and validation
Lead Design-for-Test (DFT) activities, including scan insertion, ATPG, and pattern validation
Support production by working with test teams to debug and resolve test issues
Investigate and fix functional issues in post-silicon (tape-out) devices
Participate in design reviews, documentation, and quality/ISO processes

Requirements

Degree or Master's in Electrical/Electronic Engineering or related discipline
At least 5 years of relevant experience in digital IC design
Proven experience in full IC design cycle (RTL to tape-out)
Hands-on experience with:
- Verilog HDL and/or VHDL
- Logic synthesis, STA, timing closure
- DFT methodologies (scan insertion, ATPG)
Familiar with EDA tools such as Cadence or Synopsys
Knowledge in one or more of the following areas is advantageous:
- Digital or mixed-signal IC design
- Connectivity protocols (e.g., USB, UART, SPI, I²C)
- Interface-based product development
Strong problem-solving skills and ability to work collaboratively in cross-functional teams