Roles & Responsibilities
The successful candidate will be responsible of:
- DFT implementation of Scan Logic, IJTAG, MBIST Logic, Logic BIST
- Analysis to improve the testability of Digital design at Block and chip level
- Implementation of DFT logics for Digital and Mixed Signal IP
- Perform ATPG pattern generation including SSA / Transition /Path Delay and IDDQ pattern
- Perform ATPG verification and simulation playback
- Deliver high quality ATE patterns for production ATE testing
- Provide test pattern support to ATE engineering team for First Proto bring up and failure analysis in the use of ATPG test and scan/debug features
REQUIREMENTS:
- Bachelor degree or equivalent in Electrical or Computer Engineering
- Familiar with HDL design language
- Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, cshell, Perl)
- Knowledge of ASIC design is a must, and ATE test is a plus
- Strong problemsolving skills and Team player with strong communication skills
