Design Verification Intern

The position for this recruitment is part of the YES Program(Youth Interns Exchange Scheme)a flagship collaborative program focused on youth development, co-launched by the Singapore Government and Canaan.

Key Participation Information

• Target Participants: Exclusively Singaporean citizens (youth)
• Work Location: Beijing, China
• Program Details: For more authoritative information, please visit the official YES Program websitehttps://businesschina.org.sg/youth-interns-exchange-scheme-yes/

Responsibilities:

Perform chip verification for new product development.

Participate in IP- and system-level simulation verification.

Develop and maintain UVM-based verification environments according to architectural documentation.

Define and achieve functional coverage targets; improve code and functional coverage based on the verification plan.

Execute verification across gate-level and post-simulation stages; debug issues, resolve cases, and ensure verification tasks are completed at each project milestone.

Support validation requirements and contribute to successful tape-out.

Qualifications:

Major in Electrical Engineering, Microelectronics, or related field.

Solid knowledge of UVM methodology (strong advantage).

Proficiency in Verilog/System Verilog.

Strong scripting skills in at least one language: Python, Perl, Tcl, or Shell (required).