Job description
Role Overview
Lead the process engineering function for bumping fabrication, ensuring operational stability, yield optimization, technology advancement, and team development in wafer-level packaging processes.
Key Responsibilities:
Lead and manage multi-section process engineering teams across photolithography, PVD, plating, etch/clean, reflow, AOI, and metrology.
Oversee daily fab performance drive yield, quality, cycle time, and cost improvements.
Direct NPI, technology transfers, and process integration initiatives.
Implement robust process control systems (SPC, DOE, FMEA, OCAP, FDC) and promote digital/process analytics.
Mentor and develop engineers and section managers foster high-performance team culture.
Ensure adherence to EHS, quality, ISO standards, and participate in audits.
Collaborate cross-functionally with Manufacturing, Planning, Quality, IT/Automation, and customers.
Ideal Requirements:
Bachelor's or Master's degree in Engineering (Microelectronics, Materials, Chemical, Electrical, or related).
12-18 years semiconductor process experience, with 5 years in managerial/senior leadership roles.
Strong expertise in wafer bumping/WLP processes (UBM, RDL, Cu pillar, solder bump, WLCSP).
Proven success in yield improvement, technology transfer, and cost optimization.
Familiarity with major fab equipment (TEL, ASML, EVG, DISCO, SUSS).
Skilled in SPC, DOE, FMEA, data analytics, and process integration.
Strategic thinker with strong leadership, communication, and stakeholder management skills.
Ability to thrive in fast-paced, high-mix manufacturing environments.
If you would like to be considered for this opportunity, please forward a copy of your full CV to [Confidential Information]
Data provided is for recruitment purposes only. Only shortlisted candidates will be notified.
Business Registration Number : 200611680D | Licence Number : 10C5117 | EA Registration Number: R25127614
