ATE TEST ENGINEER - Scan

Job Description

. Plan and execute pattern bring-up and validation plans based on schedule
. Plan and execute on chart plans based on schedule
. Support High temperature operating life and Package qualification activities based on schedule
. Provide DIB boards design guidelines based on schedule
. Work with Package and HWI team for HW readiness based on schedule
. Work with design team for content readiness based on schedule
. ATE test program development, validation and release
. Plan and execute sample deliveries plan based on schedule
. Plan and execute yield attainment plans based on schedule
. Plan and execute test time attainment plans based on schedule
. Align test points and define Vid bucketing based on schedule
. Work with Quality to support RMA debug to meet cycle time with the customers and drive quality

improvements to meet targeted DPPM
. Qualifying OSAT for manufacturing testing
. Manufacturing, and post-manufacturing product life cycle support
. Test development experience on Verigy 93K, involving ATE test flows development and debug.
. Completed at least 2 full product cycles from Pre-silicon to Post silicon bring up, preferred.
. Unix and Windows proficiency and Java, Perl, Python scripting skills.

Job Requirements

.Practical knowledge of silicon debug using ATE, including implementation of test specifications, pattern/vector

development, and timing

.Familiarity with Scan/ATPG methodologies, hardware compression, failure mechanisms, debug processes, and AC scan development
.Experience with functional or cache resident testing
.Understanding of modern SRAM cell operation, associated debug, test, and characterization familiarity with

Memory BIST engines
.Background in analog/mixed-signal DFT for microprocessor architectures
.Experience with Verigy 93K ATE platforms, including infrastructure and methodologies for connectivity-based

testing
.Strong communication and data presentation skills
.Proficiency with diagnostic tools such as logic analyzers, voltmeters, oscilloscopes, and related equipment
.Knowledge of JTAG IEEE 1149.1 specification and hardware description languages
.Statistical analysis expertise for population means and outlier identification Pareto analysis for debug

processes
.Relevant professional experience in any of the aforementioned areas is highly valued

.Sound understanding of Computer Architecture, including pipelining, caching, x86 architecture, and PC

organization
. Proficiency in software programming (Python, Ruby, C++, Java, C, or C#) scripting languages (Perl, Ruby, shell

script, etc.)

. Experience with Lean, XP, AGILE, Scrum, or Kanban methodologies
. Familiarity with version control systems (GIT, SVN, CVS, etc.)
. Industry experience in processor test development, validation, and/or debugging
. Academic background in Computer Science, Software Engineering, Digital Logic, and Circuit Theory
. Experience with Linux/Unix and Microsoft Windows operating systems, as well as standard office applications
. Strong collaborative capabilities and experience working with geographically diverse engineering teams