Job description
Role Overview:
Responsible for end-to-end backend digital IC design, including layout, placement, routing, and physical verification for advanced SoC technologies.
Key Responsibilities:
Integrate top-down/bottom-up SoC physical design flows.
Execute P&R, extraction, physical verification, STA, and ECO.
Develop and adapt automation flows for backend processes.
Ideal Requirements:
Master's or PhD in EE, CS, Math, Physics, or related.
Strong knowledge of backend digital design and EDA tools (Genus, Innovus, Quantus, Tempus, DC, Star-RCXT, PrimeTime, PrimeRail, Voltus, Redhawk).
- Proficient in handling EDA tools across floorplan/partition/placement/CTS/route stages for SoC top-level.
Proficient in timing/physical constraints and scripting (Tcl, Perl).
If you would like to be considered for this opportunity, please forward a copy of your full CV to [Confidential Information]
Data provided is for recruitment purposes only. Only shortlisted candidates will be notified.
Business Registration Number : 200611680D | Licence Number : 10C5117 | EA Registration Number: R25127614
