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Responsibilities
1.Define and evaluate architectural features for next-generation AI inference chips. 2.Analyze Transformer and LLM workloads to identify performance, power, area, memory, and latency bottlenecks.
3.Explore AI accelerator architectures and microarchitectures, including compute arrays, memory hierarchy, NoC, DMA, scheduling, and dataflow.
4.Work on hardware-software co-design for LLM inference, including operator mapping, tiling, memory planning, and compiler-guided optimization.
5.Collaborate with algorithm, compiler, RTL, verification, and software teams to deliver implementable architecture solutions.
6.Propose novel architecture ideas and contribute to patents and technical documentation.
Qualification
1.Bachelor's degree or above in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
2.Strong knowledge of computer architecture, AI accelerators, memory hierarchy, interconnect, and performance analysis.
3.Familiarity with Transformer and LLM architecture, including attention, FFN, quantization, KV cache, prefill, and decoding.
4.Experience with compiler, MLIR/LLVM/TVM/XLA/Triton, or kernel optimization is preferred.
5.Familiarity with Verilog, SystemVerilog, VHDL, or Chisel is a plus.
6.Strong analytical, communication, collaboration, and learning skills.
7.Fresh graduates with strong fundamentals and relevant project experience are encouraged to apply.
Job ID: 147570257
Skills:
triton , Noc, Verilog, DataFlow, Tiling, LLM workloads, AI inference chips, memory hierarchy, DMA scheduling, hardware-software co-design, TVM, compiler-guided optimization, XLA, VHDL, memory planning, LLVM, Chisel, kernel optimization tools, MLIR, systemverilog, microarchitectures, AI accelerator architectures, operator mapping, compiler frameworks, compute arrays
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