static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Java, Google Cloud Platform, Saas, Cassandra, PostgreSQL, Spring Boot, Sql, Angular, Microservices, Nosql, Jenkins, React, Gcp, MySQL, MongoDB, Azure, Oracle, Kubernetes, AWS, Software-as-a-Service

Azure - AKS, Python, Sql, Github, Docker, Arm

Software Release Management, Shell scripting, Deployment Git, WLAN standards IEEE 802.11, Automation using Python

Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

synopsys primetime , Tcl, Python, Perl, SI noise analysis, AOCV, MMMC methodologies, timing exceptions, POCV, OCV, clocking methodologies