Digital Logic Design, Computer Architecture, Verilog, Python, Systemc, VHDL, System-Level Modeling, Embedded Systems, Simulink

arm architecture , Usb, DDR, Perl, Pcie, Test Plan, Scripting, Python, Shell Programming, Tcl, Arm core, GIC, SMMU, Dms, verification checks, Arm system IP, verification plan, debug methodology, SoC Verification

monte carlo , python, AI ML, Cadence Virtuoso, Spice Simulator

Azure - AKS, Python, Sql, Github, Docker, Arm

Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

Wix, C Sharp, Msi, Cloudformation, Git, Cmake, Jfrog, Groovy, DevSecOps, Github, Msbuild, Sonarqube, Shell, PowerShell, Python, Docker, Jenkins, AWS CDK, Monitoring and observability technologies, Infrastructure as Code using Terraform, GitHub Actions, SBOM, CI CD architecture and platform engineering, AWS cloud architecture and services, CodeQL

Python, Perl, AHB, JasperGold, Uvm, formal verification, VC Formal, systemverilog, APB, Axi, AMBA protocols