power optimization , static timing analysis, routing, Verilog, Synthesis, power distribution analysis, submicron process node technologies, power delivery methodologies, Power Estimation, reliability verification, formal verification, VHDL, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis

redhawk , Scripting Languages, Python, Perl, Tcl, PrimeTime PT, voltage islands, Clock Tree Synthesis CTS, HM-level PV, Tempus, STA signoff checks, Fusion Compiler FC, Voltus, Innovus, Genus, IR drop analysis, Place Route PNR, ECOs for timing convergence, Tweaker, floorplanning, PDN design, low-power design methodologies, LEC low-power checks, Physical Verification, Physical Design, STA closure

cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Skill, 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script, SDC STA and Equivalence checking, Physical Design, PnR tools like ICC2 Innovus

Power Planning, Routing optimization, floorplanning, Placement, Debugging setup hold violations, Physical Verification, Physical Design ASIC implementation, Cadence Innovus

Tcl, C, Perl, Physical Verification, Timing Closure, floorplanning, Physical Design Implementation, Clock Planning, Placement and Routing

ICV or Calibre tools, block subsystem timing closure, physical design verification, full chip floor-planning and integration, IR EM analysis and resolution, block level and full-chip physical verification methodology, block physical design PDV and IR