arm architecture , ACE lite or CHI bus protocols, CPU architecture, Coherent and non-coherent fabric IPs and protocols, PCIe Controller PHY IPs and protocols, DDR protocols, emulation constraints, pre-silicon SoC verification, Memory Controller PHY IPs, performance verification

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Low Power Verification., C Programming, SoC Verification, systemverilog, Uvm, ARM SoC, Gate Level Simulation, Coverage Closure, APB, AHB, Axi

Tcl, Python, Ovm, Vcs, Perl, Questa, Uvm, systemverilog, Modelsim

Uart, Usb, Regression Testing, C Programming, Ethernet, SVA, Assertions, Uvm, UPF, Functional Coverage, systemverilog, AMBA Protocols, AHB, CPF, APB, Axi, ARM-based SoC Verification

Mac, Switch, Pcie, 1G Ethernet, UFS, SV, XUSB, High Speed IO verification, verification tools for simulation and debug, Uvm