C, Perl, Arm, Python, RISC-V Assembly, digital Verification, Cadence SKILL, Mixed-signal Verification, Uvm, systemverilog, UVM testbench creation

SystemVerilog Assertions, Uvm, systemverilog, Synopsys verification suites

bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Axi, AMBA, Timing Constraints, ATPG, APB, Questa, microcontroller platforms, Cadence Virtuoso, AHB

Dsp, C, Java, Os, Firmware, Automation, Python, PSR, Driver, Display Validation, DPU, Hardware, FHD, Type-C, HDCP, Multi-display, VRR, HDR, 4K, 2K, Dsc, USB4, HDMI

Golang, Google Cloud Platform, Python, Sql, GenAI models, Google BigQuery

Excel, Python, Ms Word