Verilog, primetime, Fusion Compiler, Formality, Tempus, Conformal, DFT methodologies, Timing Analysis, systemverilog, RTL-to-GDSII flow, Innovus, EDA Tools, Genus, low-power design techniques

power optimization , Verilog, systemverilog, SDC synthesis, EDA Tools, Fusion Compiler, Timing signoff, Innovus, primetime, Tempus, Conformal, Formality, Genus, RTL-to-GDSII flow, Low-power design techniques