C, Verilog, automation, Scripting, coverage closure, AI-assisted workflows, RTL testbench debugging, Uvm, systemverilog

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Vcs, Tcl, Python, Perl, Testbench Architecture, Questa, Uvm, Functional Coverage, systemverilog, CHI, Ace, Xcelium, Constrained Random Verification, RISC-V architecture, Verdi, SVA, DVE, Axi

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming