rtl verification , Verilog, SoC design flow, Simulation, systemverilog, Rtl Design, Axi, digital design concepts, APB, debugging methodologies, BUS Protocols, AHB

rtl verification , Verilog, AHB, SoC design flow, debugging methodologies, systemverilog, datapath design, reset strategy, Rtl Design, clock-domain handling, timing considerations, FSM design, APB, Axi, BUS Protocols, Simulation