Vcs, Tcl, Python, Perl, Testbench Architecture, Questa, Uvm, Functional Coverage, systemverilog, CHI, Ace, Xcelium, Constrained Random Verification, RISC-V architecture, Verdi, SVA, DVE, Axi

C, Makefile, Hdl Programming, Perl, Verilog, Computer Architecture, Ruby, System Verilog, Python, AI tools, Functional Verification, UNIX software environment, logic simulation, Assembly Programming

C, Makefile, Hdl Programming, Perl, Verilog, Computer Architecture, Ruby, Python, System Verilog, AI tools, Functional Verification, UNIX software environment, simulation and debugging, logic simulation, Assembly Programming

arm architecture , RIS tools, verification methodologies and tools, CPU microarchitecture verification

C, Verilog, automation, Scripting, RTL testbench debugging, memory hierarchy, Uvm, systemverilog, Arm CPU architecture, coverage closure, coherency protocols, subsystem integration, interrupts

Python, Tcl, timing sign-off, PDV, Physical Design, place-and-route analysis, Cadence Innovus, Siemens Mentor Calibre, advanced technology nodes 5nm or lower

Shell, Perl, Vcs, Python, Xcelium, Questa, CPU Processor verification, Uvm, systemverilog, SVA