Shell, C, Perl, Verilog, Python, Tcl, EDA Tools, UVM methodology, systemverilog

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, UCIe, Uvm, systemverilog, AMBA, Axi

Usb, Spi, DDR, Jtag, Pcie, Perl, Ethernet, Python, Uvm, UPF, systemverilog, Axi, SoC verification and validation, APB, I²C, Palladium Emulation, LPDDR, I3C, CPF, AHB

boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, Gate level simulation debugging, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax

Unix, Python, Lsf, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, GenAI, cdc, Design Verification, design layout constraints, CI CD process, DesignSync, UPF, SDC, Dft, RDC, EDA Tools, Graph Neural Networks, Implementation, make, reinforcement learning, debug tools, convolutional Networks, Power-aware flows, Clocks, SW development

Perl, C Programming, Python, Control Systems, active power management, power modeling, silicon bring-up, power thermal controllers, Validation, productization, Measurement

sentinel , Ansible, AWS, Siem, Python, Azure, Gcp, Terraform, Cloud Computing, SCA, Policy as Code, Go, OPA, DevSecOps automation frameworks, Infrastructure as Code, Container Scanning, SAST, WAF configuration management