Jasper, Perl, Python, Asic verification, formal property checking tools, Synopsys Magellan, systemverilog, Cadence IEV, verification methodologies and tools, VC Formal, functional coverage, SVA

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Usb, Ovm, Soc, DDR, Pcie, Ethernet, System Verilog, Ip, Uvm, Video, MIPI, VMM, ARM Based SoC Verification, HDMI, dsi, CSI

Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi

Computer Architecture, Verilog, Uvm, systemverilog, coverage-driven verification, advanced stimulus generation

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Coverage, Assertion checkers, Uvm, MIPI, VMM, Validation plan, System Verilog HVL, Scenario creation