Materials Engineering, Lean Methodologies, Verification Protocols, CAD Packages, Six Sigma

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

C, Systemc, Nvme, Tcl, Soc Architecture, Performance Modeling, Verilog, System Verilog, Ethernet, Python, Perl, Pcie, Simulation Tools, full chip emulation, Uvm, RAS architectures, cshell, AHB, digital design verification, boot security, Axi, power management, BUS Protocols

Ansys, Ms Office, Solid Modeling, Aerospace, CAD, Six Sigma Black Belt

Version Control Systems, Tcl, Verilog, static timing analysis, Perl, Git, Shell, Perforce, Python, Scripting Languages, AHB, LEC, systemverilog, EDA Tools, LINT, Rtl Design, Synthesis, APB, Axi, SoC Architecture Design, SoC Integration, cdc, formal verification, AMBA protocols, Simulation

Intel/ Altera development tool chains, FPGA Design, cdc, Reverse Engineering, test bench for verification, RTL design using VHDL/verilog, Design of IP cores-protocols-HDLC-SPI, STA and other timing considerations