Phase Interpolator, Cadence tool experience, CAD tools for circuit simulation, CMOS design, Bias and Bandgap Voltage Regulators, SERDES, jitter and signal equalization techniques, High Speed Clock Distribution, Low jitter PLL, layout and physical verification

Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Physical verifications, Pll, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check

Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Pll, Physical verifications, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check

Driver, Receiver, CMOS design, Physical Verification, High Speed Clock Distribution, Layout, Low jitter PLL, SERDES, Serializer, Deserializer, jitter and signal equalization techniques, Phase Interpolator, Bias and Bandgap Voltage Regulators, Circuit Simulation

routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

Python, Circuit Simulation, MC analysis, Sram

redhawk , Scripting, Tcl, Perl, routing, Shell, Python, floorplanning, Physical Verification, variability analysis, EDA Tools, EM, Ir, Placement, primetime, Synopsys ICC2, Cadence Innovus, CTS, low-power design, automation skills, Voltus, Si, Timing Closure, ASIC SOC physical design implementation, StarRC